1. Field of the Invention
The invention generally relates to circuits, and particularly to clock and data recovery circuits.
2. Description of the Related Art
A host and a device typically transmit and receive data to and from each other. For example, in a personal computer or in an enterprise storage system, a disk drive controller (host) is typically coupled to a disk drive (device) using a standardized interface. For example, the host and the device can be operatively connected by a Serial Advanced Technology Attachment (SATA) interface, by a Serial Attached SCSI (SAS) interface, and the like.
The SAS interface standard imposes relatively strict system level requirements on both the host and the device. For example, the system reference clock frequency range is limited to ±100 parts per million (ppm). FIG. 1 illustrates a host and device connection by a SAS interface. Since the total frequency offset between the host and the device is only ±200 ppm, a single loop clock and data recovery system can be used. FIG. 2 illustrates a conventional single loop clock and data recovery system.
To assist with the compliance of electromagnetic emissions standards, the SATA interface standard permits the data to be modulated using a spread spectrum clocking (SSC) scheme. FIG. 3 illustrates a SSC modulation scheme in which a triangular waveform is used to vary the frequency of the data between 0 and −5000 ppm from a nominal frequency. The frequency range of the waveform used to SSC modulate the data is typically about 30 kHz to about 33 kHz. In addition to the spread spectrum modulation, a SATA system should be able to tolerate another ±350 ppm frequency offset from each of the host side and the device side as illustrated in FIG. 4.
The single loop clock and data recovery circuit illustrated in FIG. 2 is typically not able to recover spread spectrum clocking (SSC) modulated information with relatively good jitter tolerance. FIG. 5 illustrates phase tracking for a single loop clock and data recovery circuit.
The maximum phase error PEfreq(max) introduced by a frequency offset can be calculated using Equation 1.PEfreq(max)=Fdata*PPM(max)*Time(UI)  Equation 1
In Equation 1, Fdata represents the rate of the clock embedded in the data, and PPM(max) represents the maximum frequency offset. “UI” indicates the unit interval over which the phase error is calculated.
The clock and data recovery tracking phase TPCDRU can be calculated using Equation 2.TPCDRU=Fud*Δp*Time(UI)  Equation 2
In Equation 2, Fud represents the phase update rate, and Δp represents the phase update step.
Equation 3 expresses a calculation for a phase update rate Fud to compensate for the phase error induced by a frequency offset.
                              F                      u            ⁢                                                  ⁢            d                          =                                            F              data                        ⨯            PPM                                Δ            ⁢            p                                              Equation        ⁢                                  ⁢        3            
Using a first-generation SATA interface (1.5 Gbps data rate) as an illustrative example and selecting Δp to be 1/32 UI, the phase update rate Fud should be at least 240 MHz as illustrated in the following equations. As the conventional phase tracking loop illustrated in FIG. 2 is predominantly occupied tracking the phase error induced by this relatively large frequency offset, high frequency phase jitter performance suffers. This degrades the overall system jitter tolerance performance.Fdata=1.5GHz  Equation 4PPM=5000ppm  Equation 5Δp= 1/32UI  Equation 6
                              F                      u            ⁢                                                  ⁢            d                          =                                                            F                data                            ⨯              PPM                                      Δ              ⁢              p                                =                      240            ⁢                                                  ⁢            MHz                                              Equation        ⁢                                  ⁢        7            
To recover spread spectrum modulated data and/or data with a relatively large static frequency offset with respect to a local reference clock, a more complex clock and data recovery circuit is typically used than the circuit illustrated in FIG. 2.
FIG. 6 illustrates a conventional dual loop clock and data recovery circuit with a single accumulator range. The dual loop clock and data recovery circuit has an additional loop for frequency tracking over the circuit illustrated in FIG. 2. The frequency tracking loop is used to track frequency offset induced phase errors, which permits the phase tracking loop to track high frequency phase noise relatively efficiently. The clock and data recovery system depicted in FIG. 6 can be sensitive to initial conditions, which can prevent the clock recover system from achieving phase lock with the received data. When the initial conditions of the system are such that an offset from the frequency tracking path exceeds a correctable range of the phase tracking path, the clock and data recovery system can have difficulty achieving phase lock.
FIG. 7 illustrates a conventional triple loop clock and data recovery circuit having a frequency tracking loop, a phase tracking loop, and an initial frequency setting loop. The analog implementation of the triple loop clock recovery system of FIG. 7 typically consumes relatively large amounts of power, which makes it undesirable for use where power budgets are relatively small.
FIG. 8 illustrates a conventional dual loop clock and data recovery system with a single accumulator range with accumulator limits of A and D shown in FIG. 8. The dual-loop architecture includes two tracking paths. A phase tracking path is used to track phase differences between the local clock reference signal and the received data signal. A frequency tracking path including an accumulator 802 tracks frequency offsets between the received data signal and the local clock reference. This permits the clock and data recovery system to track relatively wide frequency offsets without degrading the jitter tolerance of the system.
A value representing the frequency offset is stored in a register D of the accumulator 802. When the accumulator value tracks the frequency offset between the received data signal and the local clock reference signal, the system can be referred to as “locked”. Otherwise, if the accumulator value drifts to a value that is out of range with respect to the frequency offset of the incoming data signal, the system can be referred to as “unlocked.”
The clock information is embedded in the received data. For a multi-purpose/multi-application device, the frequency variation of the incoming clock can initially be unknown to the receiver or system. The frequency variation can include fixed offsets, frequency ranges, and the like. For example, the device may have to be compatible with different protocols such as Serial Advance Technology Attachment (SATA), Serial Attached SCSI (SAS), and the like. In the SATA standard, the received data may optionally be modulated by a low frequency profile such as the triangular waveform illustrated in FIG. 3. In this case, the frequency of the embedded clock can be close to or vary by as much as 5700 ppm with respect to the local clock reference signal.
For a clock and data recovery system to recover an embedded clock signal from the received data signal properly, the accumulator range of the frequency tracking path should be at least large enough to support the largest frequency offset possible for all protocols specified for the clock and data recovery system. For example, if the clock and data recovery circuit is to be used in devices that support both the SATA and SAS protocols, the accumulator should be able to cover a 5000 ppm spread spectrum down spreading plus ±350 ppm transmitter/receiver reference clock offsets as specified by SATA standard. Such a device typically uses a clock and data recovery system specified to track data with offsets ranging from +700 ppm to −5700 ppm.
When the frequency of the received data signal is spread spectrum modulated, such as permissible by the SATA protocol, the frequency of the incoming data signal (the received data signal) should periodically fall within the locking range of the system regardless of the initial value of the accumulator, and the system should eventually attain phase lock.
However, if the frequency of the received data signal is not modulated and the value stored in the accumulator is such that a resulting frequency offset exceeds a correctable range of the phase tracking path of the clock and data recovery system, the system can have difficulty achieving lock. For example, the clock and data recovery system can be specified to cover a frequency offset of +700 ppm to −5700 ppm to be compliant with the SATA standard. The limits of the accumulator range can be represented by A and D, where A represents +700 ppm of frequency offset, and D represents −5700 ppm of frequency offset. Assuming the accumulator initial value has drifted to limit D, the recovered clock frequency forced by the frequency tracking path can be calculated by Equation 8.Frclk(D)=(1−5700ppm)Fnom  Equation 8
In Equation 8, Fnom represents the frequency of the receiver system clock signal. If the received data signal is not spread-spectrum modulated, the embedded clock frequency is approximately Fnom. With the accumulator at limit D, the clock and data recovery system is stressed by approximately a 5700 ppm frequency offset as expressed by Equation 8.
FIG. 9 illustrates the clock and data phase error accumulation due to frequency offset in which PPM represents a frequency offset (expressed in ppm) between the frequency Frclk of the recovered clock signal and the frequency Fnom of the local clock reference.
In a real-life system, a phase tracking loop typically includes a contribution from a gain stage of 1/N, where N is the number of clock cycles per update of the clock phase by Δp unit intervals (UI). In the illustrated example of FIG. 9, where the rising edge of the clock starts in the middle of the data period at time T1, the phase error increases by about PPM UI per clock cycle, e.g., PPM*N*T. After N clock cycles, the clock and data phase error is N*PPM UI. If the phase update step Δp is at least as large as the accumulated phase error N*PPM as shown in Equation 9 (both expressed in unit intervals), the clock and data recovery system should be able to maintain phase lock.Δp≧N*PPM  Equation 9
For example, in a system where N is 16, and the phase update step Δp is 1/32 UI, the maximum offset for the frequency offset PPM for which the phase tracking loop is expected to be able to achieve lock is calculated in Equation 10.PPM≦Δp/N=1953ppm  Equation 10
For example, for a dual-loop clock and data recovery system characterized by the relationship expressed in Equation 10, achieving lock when a frequency offset of more than about 2000 ppm exists can be problematic.